QUESTION BANK
Unit – I
Boolean algebra and Logic Gates
Part A
1. Find the hexadecimal equivalent of the decimal number 256
2. What is meant by weighted and non-weighted coding?
3. Find the decimal equivalent of (346)7
4. Convert 231.3 4 to base 7 .
5. Express x+yz as the sum of minterms
6. What is prime implicant?
7. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D=1
8. Implement AND gate and OR gate using NAND gate
9. What is the exact number of bytes in a system that contains (a) 32K byte, (b) 64M bytes, and (c) 6.4G byte?
10. List the truth table of the function: F = x y + x y' + y 'z
Part B
1. (a) Prove that (x1+x2).(x1'. x3'+x3) (x2' + x1.x3) =x1'x2 (b) Simplify using K-map to obtain a minimum POS expression: (A' + B'+C+D) (A+B'+C+D) (A+B+C+D') (A+B+C'+D') (A'+B+C'+D') (A+B+C'+D)
2. Find an expression for the following function using Quine McCluscky method F= (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30) 3 State and Prove the theorems of Boolean algebra with illustration
4. Find the MSP representation for F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method Draw the circuit of the minimal expression using only NAND gates
5. (a) Explain about common postulates used to formulates various algebraic structures (b) Given the following Boolean function F= A"C + A'B + AB'C + BC Express it in sum of minterms & Find the minimal SOP expression
Unit – II
Combinational Logic
Part A
1. How will you build a full adder using 2 half adders and an OR gate?
2. Draw 4 bit binary parallel adder
3. Write down the truth table of a full sub tractor
4. Define Combinational circuits
5. Define Half and Full adder
6. Define HDL
7. What do you mean by carry propagation delay?
8. What is code converter? 9. What do you mean by test bench?
10. Give short notes on simulation versus synthesis
Part B
1 Design a 4 bit magnitude comparator to compare two 4 bit number
2 Construct a combinational circuit to convert given binary coded decimal number into an Excess
3 code for example when the input to the gate is 0110 then the circuit should
generate output as 1001 3. (a) Draw the logic diagram of a *-bit 7483 adder (b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor
4. Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 codes
5. Derive the simplest possible expression for driving segment "a" through 'g' in an 8421 BCD to seven segment decoder for decimal digits 0 through 9 .Output should be active high (Decimal 6 should be displayed as 6 and decimal 9 as 9)
Unit – III
Design with MSI Devices
Part A
1. What is a decoder and obtain the relation between the number of inputs 'n' and outputs 'm' of a decoder?
2. Using a single IC 7485 ; draw the logic diagram of a 4 bit comparator
3. Write the short notes on priority encoder
4. What is multiplexer? Draw the logic diagram of8 to 1 line multiplexer
5. Write the HDL description of the circuit specified by the following Boolean function X=AB+ACD+BC'
6. Distinguish between PAL and PLA
7. Give the classification of memory
8. What is Hamming code?
9. List the basic types of programmable logic devices
10. Compare static RAMs and dynamic RAMs
Part B
1. Explain the operation of 4 to 10 line decoder with necessary logic diagram
2.(i)Implement the following with a multiplexer
F(A,B,C)=(1,2,4,5) (8marks)
(ii)What is microprogrammed control unit? Explain the different types of ROM.(8 marks)
3. Implement the switching functions: Z1 = ab'd'e + a'b'c'e' + bc + de , Z2 = a'c'e, Z3 = bc +de+c'd'e'+bd and Z4 = a'c'e +ce Using a 5*8*4 PLA
4 .Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array 5.Design a combinational circuit using a ROM ,that accepts a 3- bit number and generates an output binary number equal to the square of the given input number
Unit – IV
Synchronous Sequential Logic
Part A
1. Derive the characteristic equation of a D flip flop
2. Distinguish between combinational and sequential logic circuits
3. What are the various types of triggering of flip-flops?
4. What is race round condition? How it is avoided?
5. What is the primary disadvantage of an asynchronous counter?
6. Compare Moore and Mealy models
7. Distinguish between synchronous and asynchronous sequential logic circuits
8. How will you convert a JK flip flop into a D flip flop
9. What is mean by the term 'edge triggered'?
10. List the basic types of shift registers in terms of data movement.
Part B
1.Design a 3 bit binary Up-Down counter.
2.Design a decade up counter using JK flip-flop.
3.(i) Differentiate combinational and sequential circuits. (6)
(ii) Explain in detail the following: (10)
I) Serial in serial out shift register
II) Parallel in parallel out shift register
4. (a) What is race around condition? How is it avoided? (b) Draw the schematic diagram of Master slave JK FF and input and output waveforms.Discuss how it prevents race around condition
5. Explain the operation of JK and clocked JK flip-flops with suitable diagrams
6. (a)Using SR flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 …………. (b) Draw as asynchronous 4 bit up-down counter and explain its working
Unit – V
Asynchronous Sequential Logic
Part A
1. Distinguish between fundamental mode and pulse mode operation of asynchronous sequential circuits
2. What is meant by Race?
3. What is meant by race condition in digital circuit?
4. What are races and cycles?
5. What is the significance of state assignment?
6. What are Hazards?
7. Define static 1 hazard, static 0 hazards, and dynamic hazard?
8. Describe how to detect and eliminate hazards from an asynchronous network?
9. How to eliminate the hazard?
10. Draw the wave forms showing static 1 hazard?
Part B
1. What is the objective of state assignment in asynchronous circuit? Give hazard – free realization for the following Boolean function f(A,B,C,D) = M(0,2,6,7,8,10,12)
2. Summarize the design procedure for asynchronous sequential circuit a. Discuss on Hazards and races b. What do you know on hardware descriptive languages?
3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z Wherever Y is 1, input X is transferred to Z .When Y is 0; the output does not change for any change in X.Use SR latch for implementation of the circuit
4. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock .the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output
5. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X.
Unit – I
Boolean algebra and Logic Gates
Part A
1. Find the hexadecimal equivalent of the decimal number 256
2. What is meant by weighted and non-weighted coding?
3. Find the decimal equivalent of (346)7
4. Convert 231.3 4 to base 7 .
5. Express x+yz as the sum of minterms
6. What is prime implicant?
7. Find the value of X = A B C (A+D) if A=0; B=1; C=1 and D=1
8. Implement AND gate and OR gate using NAND gate
9. What is the exact number of bytes in a system that contains (a) 32K byte, (b) 64M bytes, and (c) 6.4G byte?
10. List the truth table of the function: F = x y + x y' + y 'z
Part B
1. (a) Prove that (x1+x2).(x1'. x3'+x3) (x2' + x1.x3) =x1'x2 (b) Simplify using K-map to obtain a minimum POS expression: (A' + B'+C+D) (A+B'+C+D) (A+B+C+D') (A+B+C'+D') (A'+B+C'+D') (A+B+C'+D)
2. Find an expression for the following function using Quine McCluscky method F= (0, 2, 3,5,7,9,11,13,14,16,18,24,26,28,30) 3 State and Prove the theorems of Boolean algebra with illustration
4. Find the MSP representation for F(A,B,C,D,E) = _m(1,4,6,10,20,22,24,26) + _d (0,11,16,27) using K-Map method Draw the circuit of the minimal expression using only NAND gates
5. (a) Explain about common postulates used to formulates various algebraic structures (b) Given the following Boolean function F= A"C + A'B + AB'C + BC Express it in sum of minterms & Find the minimal SOP expression
Unit – II
Combinational Logic
Part A
1. How will you build a full adder using 2 half adders and an OR gate?
2. Draw 4 bit binary parallel adder
3. Write down the truth table of a full sub tractor
4. Define Combinational circuits
5. Define Half and Full adder
6. Define HDL
7. What do you mean by carry propagation delay?
8. What is code converter? 9. What do you mean by test bench?
10. Give short notes on simulation versus synthesis
Part B
1 Design a 4 bit magnitude comparator to compare two 4 bit number
2 Construct a combinational circuit to convert given binary coded decimal number into an Excess
3 code for example when the input to the gate is 0110 then the circuit should
generate output as 1001 3. (a) Draw the logic diagram of a *-bit 7483 adder (b) Using a single 7483, Draw the logic diagram of a 4 bit adder/sub tractor
4. Design a combinational circuit which accepts 3 bit binary number and converts its equivalent excess 3 codes
5. Derive the simplest possible expression for driving segment "a" through 'g' in an 8421 BCD to seven segment decoder for decimal digits 0 through 9 .Output should be active high (Decimal 6 should be displayed as 6 and decimal 9 as 9)
Unit – III
Design with MSI Devices
Part A
1. What is a decoder and obtain the relation between the number of inputs 'n' and outputs 'm' of a decoder?
2. Using a single IC 7485 ; draw the logic diagram of a 4 bit comparator
3. Write the short notes on priority encoder
4. What is multiplexer? Draw the logic diagram of8 to 1 line multiplexer
5. Write the HDL description of the circuit specified by the following Boolean function X=AB+ACD+BC'
6. Distinguish between PAL and PLA
7. Give the classification of memory
8. What is Hamming code?
9. List the basic types of programmable logic devices
10. Compare static RAMs and dynamic RAMs
Part B
1. Explain the operation of 4 to 10 line decoder with necessary logic diagram
2.(i)Implement the following with a multiplexer
F(A,B,C)=(1,2,4,5) (8marks)
(ii)What is microprogrammed control unit? Explain the different types of ROM.(8 marks)
3. Implement the switching functions: Z1 = ab'd'e + a'b'c'e' + bc + de , Z2 = a'c'e, Z3 = bc +de+c'd'e'+bd and Z4 = a'c'e +ce Using a 5*8*4 PLA
4 .Design a switching circuit that converts a 4 bit binary code into a 4 bit Gray code using ROM array 5.Design a combinational circuit using a ROM ,that accepts a 3- bit number and generates an output binary number equal to the square of the given input number
Unit – IV
Synchronous Sequential Logic
Part A
1. Derive the characteristic equation of a D flip flop
2. Distinguish between combinational and sequential logic circuits
3. What are the various types of triggering of flip-flops?
4. What is race round condition? How it is avoided?
5. What is the primary disadvantage of an asynchronous counter?
6. Compare Moore and Mealy models
7. Distinguish between synchronous and asynchronous sequential logic circuits
8. How will you convert a JK flip flop into a D flip flop
9. What is mean by the term 'edge triggered'?
10. List the basic types of shift registers in terms of data movement.
Part B
1.Design a 3 bit binary Up-Down counter.
2.Design a decade up counter using JK flip-flop.
3.(i) Differentiate combinational and sequential circuits. (6)
(ii) Explain in detail the following: (10)
I) Serial in serial out shift register
II) Parallel in parallel out shift register
4. (a) What is race around condition? How is it avoided? (b) Draw the schematic diagram of Master slave JK FF and input and output waveforms.Discuss how it prevents race around condition
5. Explain the operation of JK and clocked JK flip-flops with suitable diagrams
6. (a)Using SR flip flops, design a parallel counter which counts in the sequence 000,111,101,110,001,010,000 …………. (b) Draw as asynchronous 4 bit up-down counter and explain its working
Unit – V
Asynchronous Sequential Logic
Part A
1. Distinguish between fundamental mode and pulse mode operation of asynchronous sequential circuits
2. What is meant by Race?
3. What is meant by race condition in digital circuit?
4. What are races and cycles?
5. What is the significance of state assignment?
6. What are Hazards?
7. Define static 1 hazard, static 0 hazards, and dynamic hazard?
8. Describe how to detect and eliminate hazards from an asynchronous network?
9. How to eliminate the hazard?
10. Draw the wave forms showing static 1 hazard?
Part B
1. What is the objective of state assignment in asynchronous circuit? Give hazard – free realization for the following Boolean function f(A,B,C,D) = M(0,2,6,7,8,10,12)
2. Summarize the design procedure for asynchronous sequential circuit a. Discuss on Hazards and races b. What do you know on hardware descriptive languages?
3. Design an asynchronous sequential circuit with 2 inputs X and Y and with one output Z Wherever Y is 1, input X is transferred to Z .When Y is 0; the output does not change for any change in X.Use SR latch for implementation of the circuit
4. Develop the state diagram and primitive flow table for a logic system that has 2 inputs,x and y and an output z.And reduce primitive flow table. The behavior of the circuit is stated as follows. Initially x=y=0. Whenever x=1 and y = 0 then z=1, whenever x = 0 and y = 1 then z = 0.When x=y=0 or x=y=1 no change in z ot remains in the previous state. The logic system has edge triggered inputs with out having a clock .the logic system changes state on the rising edges of the 2 inputs. Static input values are not to have any effect in changing the Z output
5. Design an asynchronous sequential circuit with two inputs X and Y and with one output Z. Whenever Y is 1, input X is transferred to Z.When Y is 0,the output does not change for any change in X.
thnks dude!!
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